Cost effective implementation of asynchronous two-level logic

被引:0
|
作者
Lemberski, Igor [1 ]
机构
[1] Baltic Int Acad, LV-1003 Riga, Latvia
关键词
asynchronous logic; minimization; two-level logic;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
We proposed the cost effective (in sense of gate number) asynchronous two-level logic. It is based on AND-OR implementation of minimized logic functions. We formulated and proved the product term minimization constraint that ensures the logic correct behaviour. We pointed out the existing tool that yields the term minimization under the constraint formulated. We processed examples and generated asynchronous two-level logic by applying our approach and known ones. The implementation complexity was compared. Using our approach, we achieved significant improvement.
引用
收藏
页码:159 / 164
页数:6
相关论文
共 50 条
  • [1] Asynchronous Two-Level Logic of Reduced Cost
    Lemberski, Igor
    Fiser, Petr
    PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2009, : 68 - +
  • [2] Accurate implementation of two-level asynchronous domain decomposition solvers
    Gbikpi-Benissan, Guillaume
    Magoules, Frederic
    ADVANCES IN ENGINEERING SOFTWARE, 2024, 193
  • [3] Complexity of two-level logic minimization
    Umans, Christopher
    Villa, Tiziano
    Sangiovanni-Vincentelli, Alberto L.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (07) : 1230 - 1246
  • [4] A fast two-level logic minimizer
    Rao, PS
    Jacob, J
    ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 528 - 533
  • [5] Two-level logic synthesis on PALs
    Kania, D
    ELECTRONICS LETTERS, 1999, 35 (11) : 879 - 880
  • [6] Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
    Stojcev, MK
    Djordjevic, GL
    Stankovic, TR
    MICROELECTRONICS RELIABILITY, 2004, 44 (01) : 173 - 178
  • [7] A power driven two-level logic optimizer
    Tseng, JM
    Jou, JY
    PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 113 - 116
  • [8] A two-level temporal logic for evolving specifications
    Schobbens, PY
    Saake, G
    Sernadas, A
    Sernadas, C
    INFORMATION PROCESSING LETTERS, 2002, 83 (03) : 167 - 172
  • [9] A new method for two-level logic minimization
    Mahmoud, HAH
    Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 1405 - 1408
  • [10] A graph approach to two-level logic minimization
    Shinozuka, K
    ESA'04 & VLSI'04, PROCEEDINGS, 2004, : 485 - 490