Management of power and performance with stress memorization technique for 45nm CMOS

被引：13

作者：

Eiho, A. ^{[1
]}

Sanuki, T. ^{[1
]}

Morifuji, E. ^{[1
]}

Iwamoto, T. ^{[2
]}

Sudo, G. ^{[1
]}

Fukasaku, K. ^{[3
]}

Ota, K. ^{[3
]}

Sawada, T. ^{[1
]}

Fuji, O. ^{[1
]}

Nii, H. ^{[1
]}

Togo, M. ^{[2
]}

Ohno, K. ^{[3
]}

Yoshida, K. ^{[1
]}

Tsuda, H. ^{[2
]}

Ito, T. ^{[1
]}

Shiozaki, Y. ^{[1
]}

Fuji, N. ^{[1
]}

Yamazaki, H. ^{[1
]}

Nakazawa, M. ^{[3
]}

Iwasa, S. ^{[1
]}

Muramatsu, S. ^{[2
]}

Nagaoka, K. ^{[3
]}

Iwai, M. ^{[1
]}

Ikeda, M. ^{[2
]}

Saito, M. ^{[3
]}

Naruse, H. ^{[1
]}

Enomoto, Y. ^{[3
]}

Kitano ^{[2
]}

Yamada, S. ^{[1
]}

Imai, K. ^{[2
]}

Nagashima, N. ^{[3
]}

Kuwata, T. ^{[2
]}

Matsuoka, F. ^{[1
]}

机构：

[1] Toshiba Co Ltd, Adv CMOS Technol Grp, Adv Log Technol Dept, Syst LSI Div,Isogo Ku, 8 Shinsugita Cho, Yokohama, Kanagawa 2102582, Japan

[2] NEC Elect Corp, Isogo Ku, Yokohama, Kanagawa 2102582, Japan

[3] Sony Corp, Isogo Ku, Yokohama, Kanagawa 2102582, Japan

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339699

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule(190nm) in 45nm technology node.

引用

页码：218 / +

页数：2

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