Comprehensive analysis of the impact of via design on high-speed signal integrity

被引：0

作者：

Chang, Weng Yew Richard ^{[1
]}

See, Kye Yak ^{[2
]}

Chua, Eng Kee ^{[3
]}

机构：

[1] DSO Natl Labs, Guided Syst Div, 20 Sci Pk Dr, Singapore 118230, Singapore

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Nanyang Ave, Singapore 639798, Singapore

[3] Inst High Performance Comp, Eneg Software & Applicat, Singapore 117528, Singapore

来源：

2007 9TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In all modern high-speed digital board designs, every slightest discontinuity on the board has to be considered carefully, especially the vias, which are abundantly used in digital design. As frequency increases and signal rise time reduces, via causes impedance discontinuities resulting in signal reflections and hence deterioration of signal integrity (SI) and system performance. The paper carries cut a comprehensive study of the impacts of various via design parameters on SI using a fall-wave electromagnetic simulator (CST microwave suite). The design parameters under study are via diameter, via height and the excess via stub in a multilayer PCB. The study allows high-speed digital designers to have a more in-depth assessment of via design and its effect on SI performance.

引用

页码：262 / +

页数：2

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