Device and process integration for a 0.55 mu m channel length CMOS device

被引:0
|
作者
Waldo, WG [1 ]
Turkman, R [1 ]
Brownson, R [1 ]
机构
[1] MOTOROLA INC,AUSTIN,TX 78721
关键词
device integration; process integration; triple layer metal; z scaling; punchthrough leakage; interconnect delay;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:124 / 135
页数:12
相关论文
共 50 条
  • [31] Optimization of LDMOS-SCR Device For ESD Protection Based On 0.5μm CMOS Process
    Jin, Xiangliang
    Wang, Yang
    Zhong, Zeyu
    2019 12TH INTERNATIONAL WORKSHOP ON THE ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS (EMC COMPO 2019), 2019, : 195 - 197
  • [32] Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process
    Jianwei Wu
    Zongguang Yu
    Genshen Hong
    Rubin Xie
    Journal of Semiconductors, 2020, 41 (12) : 61 - 68
  • [33] Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process
    Jianwei Wu
    Zongguang Yu
    Genshen Hong
    Rubin Xie
    Journal of Semiconductors, 2020, (12) : 61 - 68
  • [34] Multi-voltage device integration technique for 0.5 μ m BiCMOS & DMOS process
    Terashima, T
    Yamamoto, F
    Hatasako, K
    12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS - PROCEEDINGS, 2000, : 331 - 334
  • [35] Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process
    Wu, Jianwei
    Yu, Zongguang
    Hong, Genshen
    Xie, Rubin
    JOURNAL OF SEMICONDUCTORS, 2020, 41 (12)
  • [36] A BURIED-CHANNEL CHARGE-COUPLED DEVICE WITH NONOVERLAPPING GATE STRUCTURE FOR A CMOS BCCD PROCESS
    WARMERDAM, L
    WALLINGA, H
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1992, 7 (05) : 658 - 663
  • [37] QuickLogic, TSMC partner for 0.5-mu m device
    不详
    COMPUTER DESIGN, 1997, 36 (02): : 61 - 61
  • [38] Application of SR lithography to 0.14 mu m device fabrication
    Sumitani, H
    Itoga, K
    Shimano, H
    Aya, S
    Yabe, H
    Hifumi, T
    Watanabe, H
    Kise, K
    Inoue, M
    Marumoto, K
    Nishioka, Y
    Abe, H
    Mizusawa, N
    Saitoh, K
    Fukuda, Y
    Uzawa, S
    ELECTRON-BEAM, X-RAY, EUV, AND ION-BEAM SUBMICROMETER LITHOGRAPHIES FOR MANUFACTURING VI, 1996, 2723 : 222 - 236
  • [39] MICROMECHANICS COMPATIBLE WITH AN 0.8 MU-M CMOS PROCESS
    BIEBL, M
    SCHEITER, T
    HIEROLD, C
    PHILIPSBORN, H
    VONPHILIPSBORN, H
    KLOSE, H
    SENSORS AND ACTUATORS A-PHYSICAL, 1995, 47 (1-3) : 593 - 597
  • [40] 1.2-MU-M PROCESS DESIGN FOR CMOS VLSIS
    MATSUNAGA, JI
    MATSUKAWA, N
    HASHIMOTO, K
    NAKASE, M
    NOZAWA, H
    KOHYAMA, S
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1983, 130 (03) : C97 - C97