Threshold voltage spread in flash memories under a constant ΔQ erasing scheme

被引：1

作者：

Chimenton, A ^{[1
]}

Pellati, P ^{[1
]}

Olivo, P ^{[1
]}

机构：

[1] Univ Ferrara, Dipartimento Ingn, I-44100 Ferrara, Italy

来源：

MICROELECTRONIC ENGINEERING | 2001年 / 59卷 / 1-4期

关键词：

semiconductor memories; flash memories; integrated circuit reliability; erasing operations; reliability;

D O I：

10.1016/S0167-9317(01)00622-0

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new erasing scheme for Flash memories characterized by a constant charge injected by each pulse. An analytical expression for the erased threshold voltage as a function of electrical, technological and physical parameters shows their impact on the erased threshold distribution spread. The dynamics of threshold distributions of entire memory sectors is analyzed and the attention is focused on its independence of the initial threshold voltage and on the creation and evolution of the distribution spread, (C) 2001 Elsevier Science BY All rights reserved.

引用

页码：197 / 201

页数：5

共 43 条

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[43] A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with ΔVTH=1/6ΔVERASE for Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories
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