A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm

被引:3
|
作者
Chen, Wei-Ting [1 ]
Chen, Ren-Der [2 ]
Chen, Pei-Yin [1 ]
Hsiao, Yu-Che [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Comp Sci & Informat Engn, Digital Integrated Circuit Design Lab, Tainan 70101, Taiwan
[2] Natl Changhua Univ Educ, Dept Comp Sci & Informat Engn, Changhua 500, Taiwan
关键词
Sorting; Indexes; Computer architecture; Registers; Hardware; Arrays; Complexity theory; hardware; bidirectional; very large-scale integration (VLSI); HIGH-THROUGHPUT; DESIGN;
D O I
10.1109/TCSI.2020.3048955
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high- and low-index parts of our architecture. The first auxiliary method is boundary finding, which shortens the range for index searching by finding the boundaries of the range. The second auxiliary method is queue storing, which stores each useful index in a queue in advance to reduce the number of miss cycles during index searching. The performance of our architecture highly depends on the distribution of input data. For each set of input data to be sorted, five Gaussian distributions of the input data and four standard derivations for each distribution were adopted in our experiments. The results show that at the expense of some additional area cost, the number of sorting cycles and the energy consumption are significantly reduced by our method.
引用
收藏
页码:1493 / 1506
页数:14
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