Asynchronous cryptographic hardware design

被引:3
|
作者
Teifel, John [1 ]
机构
[1] Sandia Natl Labs, Albuquerque, NM 87185 USA
来源
2006: 40th Annual IEEE International Carnahan Conferences Security Technology, Proceedings | 2006年
关键词
asynchronous logic; DES cryptography; low-power circuits;
D O I
10.1109/CCST.2006.313454
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Asynchronous integrated circuit technology provides low-power and low-noise operation for portable electronic security applications. Rather than using a global clock, asynchronous circuits employ a system of distributed handshake signals that control on-chip dataflow; reducing power consumption to only those parts of a chip actively involved in computation. Sandia has developed an automated asynchronous design flow that enables the rapid development of these asynchronous ASICs. This paper describes the design of asynchronous DES encryption circuits using this flow, and evaluates their performance against standard synchronous implementations.
引用
收藏
页码:221 / 227
页数:7
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