Design of a CMOS T/R Switch With High Power Capability: Using Asymmetric Transistors

被引:9
|
作者
Liu, Szu-Ling [1 ,2 ,3 ]
Wu, Meng-Hsiu [1 ,2 ]
Chin, Albert [1 ,2 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30010, Taiwan
[3] Taiwan Semicond Mfg Co Ltd, Hsinchu 300, Taiwan
关键词
BVdss; insertion loss; isolation; power-handling capability;
D O I
10.1109/LMWC.2012.2227465
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single-pole double-throw transmit/receive (T/R) switch has been realized by using both conventional and asymmetric MOSFETs in a standard 0.18 mu m CMOS technology. At 2.4 and 5.8 GHz, the asymmetric-transistor based T/R switch shows 2.7 dBm and 2.3 dBm improvements in measured 1 dB compression points (P(1 dB)s) than the conventional circuit of the same circuitry and layout, respectively. This switch also has good insertion losses of 0.62/0.7 and 0.94/1.2 dB for transmit-end/receive-end modes at 2.4 and 5.8 GHz, respectively.
引用
收藏
页码:645 / 647
页数:3
相关论文
共 50 条
  • [41] A wideband 27-dBm CMOS T/R switch using stacking architecture, high substrate isolation and RF floated body
    Chu, Chun-Hsueh
    Lin, Yih-Hsia
    Chang, Da-Chiang
    Gong, Jeng
    Juang, Ying-Zong
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2009, 96 (9-10) : 989 - 1003
  • [42] A novel multi-stack device structure and its analysis for high power CMOS switch design
    Ahn, Minsik
    Lee, Chang-Ho
    Kim, Byung-Sung
    Laskar, Joy
    2007 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-6, 2007, : 1388 - +
  • [43] Highly Linear Robust RF Switch with Low Insertion Loss and High Power Handling Capability in a 65 nm CMOS Technology
    Rascher, Jochen
    Pinarello, Sandro
    Mueller, Jan-Erik
    Fischer, Georg
    Weigel, Robert
    2012 IEEE 12TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2012, : 21 - 24
  • [44] Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers
    Roy, Debapriya
    Biswas, Abhijit
    IET CIRCUITS DEVICES & SYSTEMS, 2019, 13 (04) : 510 - 518
  • [45] New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
    Ker, MD
    Chen, TY
    Chang, HH
    MICROELECTRONICS RELIABILITY, 1999, 39 (03) : 415 - 424
  • [46] High isolation and high power of 0.13 μm CMOS SPDT switch using deep-N-well transistors and floating-body technique in K-band
    Wang, Zongxiang
    Cheng, Guoxiao
    Kang, Wei
    Li, Zekun
    Chen, Jixin
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2023, 65 (08) : 2126 - 2131
  • [47] High gain and high efficiency CMOS power amplifier using multiple design techniques
    Kim, K. -J.
    Lim, T.
    Ahn, K. H.
    Yu, J. -W.
    ELECTRONICS LETTERS, 2011, 47 (10) : 601 - 602
  • [48] SOME DESIGN CONSIDERATIONS OF HIGH POWER TRANSISTORS
    KANNAM, PJ
    NEW, TC
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1967, 23 (01) : 25 - &
  • [49] Design of Cascoded Switch for DC/DC Buck Converter Using 0.13 μm Low Power CMOS
    Yean, Eric Chew Choon
    Noh, Norlaili Mohd.
    2016 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL, ELECTRONIC AND SYSTEMS ENGINEERING (ICAEES), 2016, : 393 - 399
  • [50] W-Band Asymmetric CMOS Switch Using Inductive Matching Technique
    Kwon, Jaehyun
    Park, Changkun
    IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS, 2024, 34 (08): : 1007 - 1010