A New Resistance Model for a Schottky Barrier Diode in CMOS Including N-well Thickness Effect

被引：2

作者：

Lee, Jaelin ^{[1
]}

Kim, Suna ^{[1
]}

Hong, Jong-Phil ^{[2
]}

Lee, Sang-Gug ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea

[2] Chungbuk Natl Univ, Dept Elect Engn, Cheongju, South Korea

来源：

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2013年 / 13卷 / 04期

基金：

新加坡国家研究基金会;

关键词：

CMOS; capacitance; cut-off frequency; n-well thickness; resistance; Schottky barrier diodes;

D O I：

10.5573/JSTS.2013.13.4.381

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a 0.13 mu m CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD

引用

页码：381 / 386

页数：6

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