Low Power Comparator with Offset Cancellation Technique for Flash ADC

被引：0
|
作者：
Nasrollahpour, M. [1 ]
Sreekumar, R. [1 ]
Hamedi-Hagh, S. [1 ]
机构：
[1] San Jose State Univ, RFIC Lab, San Jose, CA 95192 USA
来源：
2017 14TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD) | 2017年
关键词：
flash ADC; comparator; low offset; Low Power;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works on a 1 GHz sampling frequency and is developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the offset and kickback noise. The comparator is implemented in a 5-bit Flash Analog to Digital converter (ADC) and the overall measured power consumption from 1 V power supply is 568 mu W. The proposed ADC can convert the analog input to digital output with 4.62 bits ENOB in Nyquist input frequency whilst the SNDR and SFDR are 29.6 dB and 42.4 dB, respectively.
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页数：4
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