Low Complexity and Low Power Multiplierless FIR Filter Implementation

For the implementation of multiplierless FIR filters, the product accumulation block (PAB) in the transposed direct form (TDF) structure has been ignored for a long time. In this work, the hardware complexity and power consumption of the PAB is investigated. It is shown that the PAB contributes the majority of hardware complexity and power consumption in multiplierless FIR filter circuits. Implementation methods for the PAB are proposed to reduce the overall hardware complexity or power consumption of multiplierless FIR filters. Experimental results show that the overall hardware complexity and power consumption can be reduced significantly.