Multi-level Reliability Simulation for IC Design

被引:0
|
作者
Sutaria, Ketul [1 ]
Velamala, Jyothi [1 ]
Cao, Yu [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85287 USA
关键词
MODEL;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.
引用
收藏
页码:130 / 133
页数:4
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