Electrical Design and Performance of a Multichip Module on a Silicon Interposer

被引:0
|
作者
Baez, Franklin M. [1 ]
Cranmer, Mike
Shapiro, Mike
Audet, Jean
Berger, Dan
Sprogis, Ed
Collins, Chris
Iyer, Subramania
机构
[1] IBM Corp, Syst & Technol Grp, Worldwide Packaging Dept, 2070 Route 52, East Fishkill, NY 12533 USA
来源
2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS | 2012年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A multichip module package has been designed in IBM's silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections < 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.
引用
收藏
页码:303 / 306
页数:4
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