Design of Direct Digital Frequency Synthesizer with the Technique of Segmenting in Quarter Wave Symmetry

被引：0

作者：

Karpagavalli, S. ^{[1
]}

Hariharan, K. ^{[1
]}

Dheivanai, G. ^{[1
]}

Gurupriya, M. ^{[1
]}

机构：

[1] Thiagarajar Coll Engn, ECE Dept, Madurai, Tamil Nadu, India

来源：

INTERNATIONAL CONFERENCE ON COMPUTER NETWORKS AND COMMUNICATION TECHNOLOGIES (ICCNCT 2018) | 2019年 / 15卷

关键词：

DDFS architecture; Read only memory; Spectral purity; ROM compression; Signal-to-noise ratio; Spurious free dynamic range; Spectrum;

D O I：

10.1007/978-981-10-8681-6_42

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In recent communication systems, Direct Digital Frequency Synthesizer (DDFS) plays dominant role in signal generation. DDFS is highly stable and highly controllable circuitry. DDFS requires read only memory (ROM) for signal generation, but usage of high ROM size leads to high power consumption and more hardware requirements. In this paper, on utilizing a quarter wave symmetry technique and storing the difference value between consecutive segments in ROM Look-up table (LUT) is proposed. The proposed architecture has reduced ROM size with beneficial effects in terms of speed and power. For 8-bit resolution SNR is of 44.92 dB and SFDR is of 50.64 dBc.

引用

页码：469 / 477

页数：9

共 50 条

[31] Design & Evaluation of Hybrid Direct Digital Synthesis/Phase Locked Loop Frequency Synthesizer
Sneath, Ben
Preethichandra, D. M. G.
2016 IEEE INTERNATIONAL INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE PROCEEDINGS, 2016, : 1138 - 1143
[32] Low-power direct digital frequency synthesizer
Curticapean, F
Niittylahti, J
PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 822 - 825
[33] Novel direct digital synthesizer design for OFDM digital receivers
Ramirez Moran, David
Gismero Menoyo, Javier
2006 EUROPEAN CONFERENCE ON WIRELESS TECHNOLOGIES, 2006, : 27 - +
[34] The analytic model for noise of direct digital frequency synthesizer
Tian, T
Wu, SJ
2001 CIE INTERNATIONAL CONFERENCE ON RADAR PROCEEDINGS, 2001, : 916 - 919
[35] Design of mixing frequency constant-current source based on direct digital synthesizer
Ju, Kang
He, Wei
He, Chuanhong
Li, Bing
Luo, Haijun
Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument, 2010, 31 (09): : 2109 - 2114
[36] Design of a compact direct digital frequency synthesizer with 12 bit amplitude and 32 bit frequency resolution
Fischer, G
Modadugu, NK
VLSI SIGNAL PROCESSING, IX, 1996, : 75 - 82
[37] A Wideband Phase Modulation Technique Adopting Fractional-N Direct Digital Frequency Synthesizer
Zhang, Bohai
You, Fei
Tong, Renbin
He, Songbai
2014 IEEE RADIO & WIRELESS SYMPOSIUM (RWS), 2014, : 214 - 216
[38] A Direct Digital Frequency Synthesizer Circuit Based on Dynamic Frequency Management
Malahnejad, Meysam
Raissi, Farshid
Mirzakuchaki, Sattar
INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS (ICSES '10): CONFERENCE PROCEEDINGS, 2010, : 225 - 228
[39] Modeling of the direct digital frequency synthesizer in a system of residual classes based on the PSPICE design system
Bazhenov, A.A.
Telecommunications and Radio Engineering (English translation of Elektrosvyaz and Radiotekhnika), 2006, 65 (04): : 311 - 317
[40] A Novel Approach to the Design of Memory-Reduced Direct Digital Frequency Synthesizer for OFDM Receiver
Li, Xiaojin
Lai, Linhui
Lei, Ao
Lai, Zongsheng
2009 WRI INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND MOBILE COMPUTING: CMC 2009, VOL I, 2009, : 298 - 302

← 1 2 3 4 5 →