Design of Direct Digital Frequency Synthesizer with the Technique of Segmenting in Quarter Wave Symmetry

In recent communication systems, Direct Digital Frequency Synthesizer (DDFS) plays dominant role in signal generation. DDFS is highly stable and highly controllable circuitry. DDFS requires read only memory (ROM) for signal generation, but usage of high ROM size leads to high power consumption and more hardware requirements. In this paper, on utilizing a quarter wave symmetry technique and storing the difference value between consecutive segments in ROM Look-up table (LUT) is proposed. The proposed architecture has reduced ROM size with beneficial effects in terms of speed and power. For 8-bit resolution SNR is of 44.92 dB and SFDR is of 50.64 dBc.