Implementation and Design of High PSRR Low Dropout Regulator

As the progress with all kinds of mixed-mode signal circuits, the requirements of power management become increasingly stringent. Therefore it takes all kinds of high-performance linear regulator to produce a very clean and stable voltage. Here cascading technique is used to increase the output impedance in this architecture. The output voltage is less susceptible to variation of input voltage, resulting in a clean and stable voltage which is used the operating voltage of internal circuits in a mixed-mode signal integrated circuit chip. This paper using the TSMC 0.35 mu m CMOS 2P4M process to implement the design of high PSRR LDO regulator, having 0.900 x 0.600mm(2) chip area, 1.34 mW consumption power. The chip supply voltage can from 2.9V to 3.3V with -106dB and -65dB PSRR at 1KHz and 100KHz, and its output voltage can stable at 1.2V and less than 2.4mV ripple voltage at maximum loading current 20 mA.