CAD tools for early timing closure in system-on-a-chip design

This paper introduces two new CAD tools, "March" and "MagusMCP," developed to partially automate the design of clock signal distribution for timing optimization and the timing constraints for systems-on-a-chip. March synthesizes flexible structures of clock distribution circuits based on flip-flop (FF) grouping and placement information. It also considers the placement and routing resource information of RAM and optimizes the delay on clock paths and clock skew. These features make it easier to satisfy timing constraints. MagusMCP automatically detects multi-cycle/false paths based on analysis that takes circuit logic into account. These tools make it possible to ease timing constraints, thus enabling early timing closure.