共 50 条
- [42] Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links 26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2008, : 17 - 22
- [45] Clock and data recovery circuit using digital phase aligner and phase interpolator IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 690 - +
- [46] A 1/8-rate clock and data recovery architecture for high-speed communication systems 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 305 - 308
- [50] Clock and carrier recovery in high-speed coherent optical communication systems SECOND INTERNATIONAL CONFERENCE ON APPLICATIONS OF OPTICS AND PHOTONICS, 2014, 9286