Delay-optimized floating point fused add-subtract unit

被引：6
|
作者：
Liu, De [1 ]
Wang, MingJiang [1 ]
Zuo, Shikai [1 ]
机构：
[1] Harbin Inst Technol, Shenzhen Grad Sch, Shenzhen 518055, Guangdong, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 17期
关键词：
floating point arithmetic; fused add-subtract unit; LOGIC;
D O I：
10.1587/elex.12.20150642
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a delay-optimized floating point fused add-subtract (FAS) unit. A FAS unit is very useful for FFT and DCT butterfly operations since it can perform addition and subtraction of two floating point numbers simultaneously. The latency of critical path is reduced by using injection-based rounding method and performing parallel exponent adjustment. The proposed FAS is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that the proposed FAS requires roughly 60% area of two discrete adders. Comparison results show that our proposed FAS unit is 30% faster and 56% less area than the fastest FAS in previous work.
引用
收藏
页数：10
相关论文
共 50 条
  • [31] Floating-point multiply-add-fused with reduced latency
    Lang, T
    Bruguera, JD
    IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (08) : 988 - 1003
  • [32] Floating-point fused multiply-add with reduced latency
    Lang, T
    Bruguera, JD
    ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 145 - 150
  • [33] Design and Implementation of Floating Point Divide-Add Fused Architecture
    Pande, Kuldeep
    Parkhi, Abhinav
    Jaykar, Shashant
    Peshattiwar, Atish
    2015 FIFTH INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT2015), 2015, : 797 - 800
  • [34] Area Effective and Speed Optimized Fused Add-Multiply Unit
    Srinitha, S.
    Sargunam, B.
    2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [35] Design of a double-precision floating-point multiply-add-fused unit with consideration of data dependence
    Li, Zhaolin
    Li, Gongqiong
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2007, : 492 - 497
  • [36] Multiple-Mode Floating-Point Multiply-Add Fused Unit for Trading Accuracy with Power Consumption
    Wu, Kun-Yi
    Liang, Chih-Yuan
    Yu, Kee-Khuan
    Kuang, Shiann-Rong
    2013 IEEE/ACIS 12TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS), 2013, : 429 - 435
  • [37] Design of an extended floating-point multiply-add-fused unit for exploiting instruction-level parallelism
    Li, Zhaolin
    Li, Gongqiong
    2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 17 - 20
  • [38] Modeling and synthesis of a modified floating point Fused Multiply-Add (FMA) Arithmetic Unit using VHDL and FPGAs
    Alghazo, J
    Nazeih, B
    CDES '05: Proceedings of the 2005 International Conference on Computer Design, 2005, : 136 - 142
  • [39] A Decimal Floating-point Fused Multiply-Add Unit with a Novel Decimal Leading-zero Anticipator
    Akkas, Ahmet
    Schulte, Michael J.
    ASAP 2011 - 22ND IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2011), 2011, : 43 - 50
  • [40] A Floating-Point Fused Dot-Product Unit
    Saleh, Hani H.
    Swartzlander, Earl E., Jr.
    2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 427 - +
12345