Efficient Test Scheduling for Reusable BIST in 3D Stacked ICs

被引：0

作者：

Mohan, Navya ^{[1
]}

Krishnan, Maya ^{[1
]}

Rai, Sudhir Kumar ^{[1
]}

MathuMeitha, M. ^{[1
]}

Sivakalyan, S. ^{[1
]}

机构：

[1] Amrita Univ, Amrita Vishwa Vidyapeetham, Amrita Sch Engn, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India

来源：

2017 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI) | 2017年

关键词：

Test scheduling; Rectangle bin packaging; Pre-bond; Post-bond; BIST; Skyline algorithm;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

VLSI testing is essential with advancing technology as it helps improve yield and enables the detection of faulty chips after manufacturing. The factors which play important roles are the power dissipation and time taken during the process of testing. BIST, Built-In Self-Test is a testing technique which enables the device to test itself. A reusable BIST is proposed which allows the usage of the same BIST for pre-bond and post-bond testing. The proposed BIST is used for testing 3D stacked ICs. Test scheduling is a critical problem that is faced while 3D stacked ICs are tested as the same tests which are performed during pre-bond might need to be performed simultaneously or so during post-bond. Here, we propose a modified Skyline algorithm to obtain an improved test schedule. The algorithm is tested on the inputs from ISCAS-85 benchmark circuits. The obtained results are compared with the results from traditional Skyline algorithm.

引用

页码：1349 / 1355

页数：7

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