Efficient Test Scheduling for Reusable BIST in 3D Stacked ICs

被引：0

作者：

Mohan, Navya ^{[1
]}

Krishnan, Maya ^{[1
]}

Rai, Sudhir Kumar ^{[1
]}

MathuMeitha, M. ^{[1
]}

Sivakalyan, S. ^{[1
]}

机构：

[1] Amrita Univ, Amrita Vishwa Vidyapeetham, Amrita Sch Engn, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India

来源：

2017 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI) | 2017年

关键词：

Test scheduling; Rectangle bin packaging; Pre-bond; Post-bond; BIST; Skyline algorithm;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

VLSI testing is essential with advancing technology as it helps improve yield and enables the detection of faulty chips after manufacturing. The factors which play important roles are the power dissipation and time taken during the process of testing. BIST, Built-In Self-Test is a testing technique which enables the device to test itself. A reusable BIST is proposed which allows the usage of the same BIST for pre-bond and post-bond testing. The proposed BIST is used for testing 3D stacked ICs. Test scheduling is a critical problem that is faced while 3D stacked ICs are tested as the same tests which are performed during pre-bond might need to be performed simultaneously or so during post-bond. Here, we propose a modified Skyline algorithm to obtain an improved test schedule. The algorithm is tested on the inputs from ISCAS-85 benchmark circuits. The obtained results are compared with the results from traditional Skyline algorithm.

引用

页码：1349 / 1355

页数：7

共 50 条

[21] An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs
Aghaee, Nima
Peng, Zebo
Eles, Petru
2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
[22] 3D stacked MEMS and ICs in a miniaturized sensor node
Taklo, Maaike M. V.
Lietaer, Nicolas
Tofteberg, Hannah
Seppanen, Timo
Ramm, Peter
Weber, Werner
DTIP 2009: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS, 2009, : 74 - +
[23] The current status and perspective in testing 3D stacked ICs
Journal of Japan Institute of Electronics Packaging, 2020, 23 (01) : 32 - 36
[24] TSV Based 3D Stacked ICs: Opportunities and Challenges
Hamdioui, Said
2012 IEEE 15TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2012, : 2 - 2
[25] Quality versus Cost Analysis for 3D Stacked ICs
Taouil, Mottaqiallah
Hamdioui, Said
Marinissen, Erik Jan
2014 IEEE 32ND VLSI TEST SYMPOSIUM (VTS), 2014,
[26] Thermal Characterization of TSV based 3D Stacked ICs
Swarup, Sahana
Tan, Sheldon X. -D.
Liu, Zao
2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 335 - 338
[27] An Inter-Layer Interconnect BIST Solution for Monolithic 3D ICs
Koneru, Abhishek
Chakrabarty, Krishnendu
2018 IEEE 36TH VLSI TEST SYMPOSIUM (VTS 2018), 2018,
[28] Uncertainty-Aware Robust Optimization of Test-Access Architectures for 3D Stacked ICs
Deutsch, Sergej
Chakrabarty, Krishnendu
Marinissen, Erik Jan
2013 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2013,
[29] A new die-level flexible design-for-test architecture for 3D stacked ICs
Zhang, Qingping
Zhan, Wenfa
Wen, Xiaoqing
INTEGRATION-THE VLSI JOURNAL, 2024, 97
[30] A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
Aghaee, Nima
Peng, Zebo
Eles, Petru
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2015, 31 (5-6): : 503 - 523

← 1 2 3 4 5 →