A Floating-Point Fused Add-Subtract Unit

被引：25
|
作者：
Saleh, Hani [1 ]
Swartzlander, Earl E., Jr. [2 ]
机构：
[1] Intel Corp, PTL1 5000 Plaza Lake Blvd,Suite 350, Austin, TX 78746 USA
[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
来源：
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2008年
关键词：
D O I：
10.1109/MWSCAS.2008.4616850
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.
引用
收藏
页码：519 / +
页数：2
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