A design platform for reconfigurable architecture and its application to watermarking system

被引:0
|
作者
Dalbouchi, Roukaya [1 ]
Elhaji, Majdi [2 ]
Zitouni, Abdelkrim [3 ]
机构
[1] Univ Sfax, Lab Elect & Microelect, Sfax, Tunisia
[2] Coll Engn, Dept Elect Engn, Al Dawadmi, Shaqra, Saudi Arabia
[3] Imam Abdulrahman Bin Faisal Univ, Coll Educ Jubail, Dept Phys, POB 12020, Jubail Ind City, Saudi Arabia
关键词
Reconfigurable architecture; Dynamic reconfiguration; Partial reconfiguration; FPGA; video watermarking; METHODOLOGY; FLOW;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a novel platform for reconfigurable architecture design. This platform contains a design that allows modeling and implementation of hardware architecture. We have nominated a generic design flow for partial and dynamic reconfigurable architecture (GDF4PDR). This flow is able to support any type of application. In addition, it is compatible with the Xilinx design flow and does not require the addition of other hardware or software elements. It is based on three elements, the reconfigurable model, the application and the mapping strategy between these elements. The comparison results show that the proposed flow is more generic and characterized by a high abstraction level modelling. The aim is to offer a platform that provides a good instance of architecture that meets compromises reconfigurations/performance. To validate the proposed platform a video watermarking application has been used. Experimental results show that the proposed design flow provides an architecture with a small reconfiguration time while ensuring optimal hardware implementation in terms of resources.
引用
收藏
页码:195 / 201
页数:7
相关论文
共 50 条
  • [41] Design flow of Reconfigurable Embedded System Architecture using LUTs/PLAs
    Singh, Sunil Kr
    Singh, Rakesh Kr
    Bhatia, M. P. S.
    2012 2ND IEEE INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND GRID COMPUTING (PDGC), 2012, : 385 - 390
  • [42] The design of a configurable and reconfigurable middleware platform
    Coulson, G
    Blair, GS
    Clarke, M
    Parlavantzas, N
    DISTRIBUTED COMPUTING, 2002, 15 (02) : 109 - 126
  • [43] The design of a configurable and reconfigurable middleware platform
    Geoff Coulson
    Gordon S. Blair
    Michael Clarke
    Nikos Parlavantzas
    Distributed Computing, 2002, 15 : 109 - 126
  • [44] VLSI design of an efficient reconfigurable FFT processor and its application
    Xiao, Hao
    Xiang, Bo
    Chen, Yun
    Zeng, Xiaoyang
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2009, 21 (02): : 209 - 213
  • [45] The architecture of the electric power system of the International Space Station and its application as a platform for power technology development
    Gietl, EB
    Gholdston, EW
    Cohen, F
    Manners, BA
    Delventhal, RA
    35TH INTERSOCIETY ENERGY CONVERSION ENGINEERING CONFERENCE & EXHIBIT (IECEC), VOLS 1 AND 2, TECHNICAL PAPERS, 2000, : 855 - 864
  • [46] Application Mapping Methodology for Reconfigurable Architecture
    Hiware, Rahul K.
    Padole, Dinesh
    PROCEEDINGS OF FIRST INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY FOR INTELLIGENT SYSTEMS: VOL 1, 2016, 50 : 11 - 15
  • [47] System design platform expands its scope
    不详
    PROFESSIONAL ENGINEERING, 2005, 18 (19) : 48 - 48
  • [48] Design of Reconfigurable Samba Bus Architecture
    Chitra, S. Hema
    Vanathi, P. T.
    Kumar, K. Naresh
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON CONTROL AUTOMATION, COMMUNICATION AND ENERGY CONSERVATION INCACEC 2009 VOLUME II, 2009, : 602 - 607
  • [49] Design and Implementation of Monitoring System Architecture for Smart Bicycle Platform
    Lee, YeongKyun
    Jeong, Jongpil
    15TH INTERNATIONAL CONFERENCE ON MOBILE SYSTEMS AND PERVASIVE COMPUTING (MOBISPC 2018) / THE 13TH INTERNATIONAL CONFERENCE ON FUTURE NETWORKS AND COMMUNICATIONS (FNC-2018) / AFFILIATED WORKSHOPS, 2018, 134 : 464 - 469
  • [50] Generic architecture platform for multiprocessor system-on-chip design
    Baghdadi, A
    Zergainoh, NE
    Lyonnard, D
    Jerraya, AA
    ARCHITECTURE AND DESIGN OF DISTRIBUTED EMBEDDED SYSTEMS, 2001, 61 : 53 - 63