A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

被引：17

作者：

Wu, CY ^{[1
]}

Chou, CY ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Integrated Circuite & Syst Lab, Hsinchu 300, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 03期

关键词：

CMOS technology; double-quadrature architecture; IEEE; 802.11a; low-noise amplifier; quadrature generator; quadrature voltage-controlled oscillator; radio frequency; receiver;

D O I：

10.1109/JSSC.2003.822779

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.

引用

页码：519 / 521

页数：3

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