Performance assessment of nanoscale double- and triple-gate FinFETs

Based on 3D simulations, we report a performance assessment of triple- and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power (LSTP) logic technologies according to ITRS 65 nm node specifications. The impact of spacer width, lateral source/drain doping gradient, aspect ratio, fin thickness and height along with gate work function on the device performance has been analysed in detail and guidelines are presented to meet the ITRS projections. The design guidelines proposed for a 65 nm node are also examined for a 45 nm node for triple- and double-gate FinFETs. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimized to achieve low values of intrinsic delay. FinFETs should be designed with a higher aspect ratio (similar to 4) along with lower values of fin thickness to achieve ITRS tat-gets for off-current and intrinsic delay. Triple-gate FinFETs show greater design flexibility in selecting important technological and device parameters as compared to double-gate devices. A design window is presented to achieve ITRS targets for the three logic technology requirements with triple- and double-gate FinFETs.