Gate stack preparation with high-k materials in a cluster tool

被引：4

作者：

De Gendt, S ^{[1
]}

Heyns, M ^{[1
]}

Conard, T ^{[1
]}

Nohira, H ^{[1
]}

Richard, O ^{[1
]}

Vandervorst, W ^{[1
]}

Caymax, M ^{[1
]}

Maes, JW ^{[1
]}

Tuominen, M ^{[1
]}

Bajolet, P ^{[1
]}

机构：

[1] IMEC VZW, Louvain, Belgium

来源：

2001 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ISSM.2001.962998

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Oxide layers of metals such as Zr and Al are possible candidates to replace SiO2 as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and wc indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al2O3, and ZrO2 layer is presented. We discuss the importance of a cluster tool for this application based on those process results.

引用

页码：395 / 398

页数：4

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