Effects of 3D Via and Die Attach on Power Integrity of a Packaged IC

被引：0
|
作者：
Lin, Yi-Chieh [1 ]
Lin, Yu-Chih [1 ]
Horng, T. -S. [1 ]
Hwang, Lih-Tyng [1 ]
机构：
[1] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung, Taiwan
来源：
2012 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC 2012) | 2012年
关键词：
Ceramics; through vias; power integrity;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
In this paper, we first investigated the effects of 3D single and multi-via(s) on power integrity of a packaged IC. Backside vias have been an essential element in MMIC technology. This paper analyzed and characterized single and multiple backside via(s). The results of this investigation can be used as a design guideline for the now very popular Through Silicon Via (TSV) technology. We also investigated how die attach techniques (vias with silver epoxy or vias with blanket Cu) affected the distribution of return ground currents. We mainly wanted to know if silver epoxy can be adequately applied in millimeter wave frequencies. This study will offer insights to future package designs that employ Cu-to-Cu bonding technology.
引用
收藏
页码：277 / 279
页数：3
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