An efficient hierarchical timing-driven steiner tree algorithm for global routing

被引:1
|
作者
Xu, JY [1 ]
Hong, XL [1 ]
Jing, T [1 ]
Cai, Y [1 ]
Gu, J [1 ]
机构
[1] Tsing Hua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
关键词
D O I
10.1109/ASPDAC.2002.994965
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing, delay during the tree construction as the goal. The algorithm uses heuristic approach to decompose the problem of minimum delay Steiner free into hierarchy and to construct the sub-trees respectively based on dynamic programming technique. Taking the net topology into consideration, we build the final routing tree by reconnecting, the sub-trees at each level recursively and then improve the connection with the objective of minimizing the delay from source to sink pins on the critical path. Meanwhile, some efficient strategies have been proposed to speed up the solving process. Experimental results are given to demonstrate the efficiency of the algorithm.
引用
收藏
页码:473 / 478
页数:4
相关论文
共 50 条
  • [31] A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout
    Koide, T
    Wakabayashi, S
    PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, 1998, : 577 - 583
  • [32] A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design
    Xu, J
    Hong, XL
    Jing, T
    Cai, YC
    Gu, J
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (12) : 3158 - 3167
  • [33] A timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout
    Koide, T
    Wakabayashi, S
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (12): : 2476 - 2484
  • [34] A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design
    Xu, JY
    Hong, XL
    Tong, J
    Cai, YC
    Jun, G
    ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 847 - 850
  • [35] An Architecture and Timing-Driven Routing Algorithm for Area-Efficient FPGAs with Time-Multiplexed Interconnects
    Liu, Hanyu
    Chen, Xiaolei
    Ha, Yajun
    2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 614 - 617
  • [36] Timing-driven global routing algorithm with pin assignment, block reshaping, and positioning for building block layout
    Koide, Tetsushi
    Wakabayashi, Shin'ichi
    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1998, : 577 - 583
  • [37] Top-down-based timing-driven Steiner tree construction with wire sizing and buffer insertion
    Yan, Jin-Tai
    Huang, Shi-Qin
    Chen, Zhi-Wei
    TENCON 2007 - 2007 IEEE REGION 10 CONFERENCE, VOLS 1-3, 2007, : 515 - 518
  • [38] Routing-aware Incremental Timing-driven Placement
    Monteiro, Jucemar
    Darav, Nima Karimpour
    Flach, Guilherme
    Fogaca, Mateus
    Reis, Ricardo
    Kennings, Andrew
    Johann, Marcelo
    Behjat, Laleh
    2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2016, : 290 - 295
  • [39] A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design
    Xu, Jingyu
    Hong, Xianlong
    Jing, Tong
    Zhang, Ling
    Gu, Jun
    INTEGRATION-THE VLSI JOURNAL, 2006, 39 (04) : 457 - 473
  • [40] A fast timing-driven routing algorithm for FPGA High Fan-out Net
    Chen, Xun
    Zhang, Min-Xuan
    Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, 2011, 33 (06): : 61 - 65