Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types

This paper describes two time-to-digital converter (TDC) architectures for fine time resolution and good linearity: integral-type and delta-sigma TDC architectures. By investigating them, the similarity and difference between TDC and ADC architectures for fine resolution but slow measurement are clarified. Our integral-type TDC architectures are inspired by the integral-type ADC, and also the time-bases of the equivalent time sampling in the sampling oscilloscope: sequential sampling and random sampling. One TDC uses a sequential sampling time-base, and the other uses a random sampling time-base. Each of them consists of two trigger circuits, a sampling flip-flop, a binary counter and additional small logic circuit. Their circuit topologies, operation principles and simulation results as well as their comparison are presented. Also our delta-sigma TDC architecture is mentioned, and comparison between the integral and delta-sigma TDC architectures is discussed.