Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types

被引：0

作者：

Kobayashi, Haruo ^{[1
]}

Machida, Kosuke ^{[1
]}

Sasaki, Yuto ^{[1
]}

Osawa, Yusuke ^{[1
]}

Zhang, Pengfei ^{[1
]}

Sha, Lei ^{[1
]}

Ozawa, Yuki ^{[1
]}

Kuwana, Anna ^{[1
]}

机构：

[1] Gunma Univ, Grad Sch Sci & Technol, Div Elect & Informat, 1-5-1 Tenjin Cho, Kiryu, Gunma 3768515, Japan

来源：

2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2019年

关键词：

D O I：

10.1109/asicon47005.2019.8983507

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes two time-to-digital converter (TDC) architectures for fine time resolution and good linearity: integral-type and delta-sigma TDC architectures. By investigating them, the similarity and difference between TDC and ADC architectures for fine resolution but slow measurement are clarified. Our integral-type TDC architectures are inspired by the integral-type ADC, and also the time-bases of the equivalent time sampling in the sampling oscilloscope: sequential sampling and random sampling. One TDC uses a sequential sampling time-base, and the other uses a random sampling time-base. Each of them consists of two trigger circuits, a sampling flip-flop, a binary counter and additional small logic circuit. Their circuit topologies, operation principles and simulation results as well as their comparison are presented. Also our delta-sigma TDC architecture is mentioned, and comparison between the integral and delta-sigma TDC architectures is discussed.

引用

页数：4

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