A 130-nm CMOS 100-Hz-6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver

被引：27
|
作者：
Goel, Ankush [1 ]
Analui, Behnam [2 ]
Hashemi, Hossein [2 ]
机构：
[1] MediaTek USA, San Jose, CA 95134 USA
[2] Univ So Calif, Dept Elect Engn Electrophys, Los Angeles, CA 90089 USA
来源：
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2012年 / 60卷 / 05期
关键词：
CMOS; receiver; RF; wideband; RADIO RECEIVER; NOISE; TUNER;
D O I：
10.1109/TMTT.2012.2190091
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is -82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.
引用
收藏
页码：1375 / 1389
页数：15
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