Comparison between Symmetrical and Asymmetrical Single Phase Multilevel Inverter with Diode-Clamped Topology

被引:22
|
作者
Nami, A. [1 ]
Zare, F. [1 ]
Ledwich, G. [1 ]
Ghosh, A. [1 ]
Blaabjerg, F. [2 ]
机构
[1] Queensland Univ Technol, Sch Engn Syst, Brisbane, Qld 4001, Australia
[2] Aalborg Univ, Aalborg, Denmark
基金
澳大利亚研究理事会;
关键词
D O I
10.1109/PESC.2008.4592393
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a different configuration based on different DC bus voltage for a diode-clamped multilevel inverter has been presented. Two different symmetrical and asymmetrical arrangements of a four-level diode clamped inverters have been compared, in order to find an optimum arrangement with lower switching losses and optimised output voltage quality. The optimised asymmetrical arrangement has been compared with a conventional four-level inverter. The comparison results show that an asymmetrical configuration can obtain more voltage levels in output voltage with same number of component compared with the conventional four-level inverter and this will lead to the reduction of harmonic content of output voltage. A predictive current control technique has been carried out to verify the viability of new configuration. The advantages of this control method are simplicity and applicability for n-level multilevel inverters, without a significant change in the control circuit.
引用
收藏
页码:2921 / +
页数:2
相关论文
共 50 条
  • [1] A Novel Three-Phase Multilevel Diode-Clamped Inverter Topology with Reduced Device Count
    Saha, Aparna
    Elrayyah, Ali
    Sozer, Yilmaz
    2016 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2016,
  • [2] A MIMO Topology with Series Outputs: An Interface between Diversified Energy Sources and Diode-Clamped Multilevel Inverter
    Behjati, Hamid
    Davoudi, Ali
    2012 TWENTY-SEVENTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC), 2012, : 1 - 6
  • [3] Single Phase Symmetrical and Asymmetrical Design of Multilevel Inverter Topology with Reduced Number of Switches
    Siddique, Marif Daula
    Mustafa, Asif
    Sarwar, Adil
    Mekhilef, Saad
    Shah, Noraisyah Binti Mohamed
    Seyedamahmousian, Mehdi
    Stojcevski, Alex
    Horan, Ben
    Ogura, Koki
    2018 IEEMA ENGINEER INFINITE CONFERENCE (ETECHNXT), 2018,
  • [4] Two-level Operation of a Diode-Clamped Multilevel Inverter
    Adam, Grain Philip
    Finney, Stephen Jon
    Williams, Barry Wayne
    Mohammed, Mohammed. T.
    IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 2010), 2010, : 1137 - 1142
  • [5] A New Diode-Clamped Multilevel Inverter for Capacitor Voltage Balancing
    Shi, Shunji
    Wang, Xiangzhou
    Zheng, Shuhua
    Xia, Fei
    PROGRESS IN ELECTROMAGNETICS RESEARCH M, 2016, 52 : 181 - 190
  • [6] Topology and Modulation for a New Multilevel Diode-Clamped Matrix Converter
    Sun, Yao
    Xiong, Wenjing
    Su, Mei
    Li, Xing
    Dan, Hanbing
    Yang, Jian
    IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (12) : 6352 - 6360
  • [7] A Sparse Multilevel Matrix Converter Based on Diode-Clamped Topology
    Khajehoddin, S. Ali
    Bakhshai, Alireza
    Jain, Praveen
    CONFERENCE RECORD OF THE 2007 IEEE INDUSTRY APPLICATIONS CONFERENCE FORTY-SECOND IAS ANNUAL MEETING, VOLS. 1-5, 2007, : 224 - 228
  • [8] Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology
    Chappa, Anilkumar
    Gupta, Shubhrata
    Sahu, Lalit Kumar
    Gautam, Shivam Prakash
    Gupta, Krishna Kumar
    IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2021, 9 (01) : 885 - 896
  • [9] Multiple-Poles Multilevel Diode-Clamped Inverter (M2DCI) Topology for Alternative Multilevel Converter
    Gabriel, Ooi H. P.
    Maswood, Ali I.
    Venkataraman, Aditya
    2012 CONFERENCE ON POWER & ENERGY - IPEC, 2012, : 497 - 502
  • [10] Harmonic elimination in diode-clamped multilevel inverter using evolutionary algorithms
    Barkati, Said
    Baghli, Lotfi
    Berkouk, El Madjid
    Boucherit, Mohamed-Seghir
    ELECTRIC POWER SYSTEMS RESEARCH, 2008, 78 (10) : 1736 - 1746