Carrier Mobility Variations in Self-aligned Germanium MOS Transistors

被引：1

作者：

Low, Y. H. ^{[1
]}

Tantraviwat, D. ^{[1
]}

Rainey, P. V. ^{[1
]}

Baine, P. T. ^{[1
]}

McNeill, D. W. ^{[1
]}

Mitchell, S. J. N. ^{[1
]}

Armstrong, B. M. ^{[1
]}

Gamble, H. S. ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Elect Elect Engn & Comp Sci, Belfast BT9 5AH, Antrim, North Ireland

来源：

ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENT | 2010年 / 28卷 / 01期

关键词：

GE;

D O I：

10.1149/1.3375587

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Tungsten gate germanium MOS transistors have been manufactured on bulk germanium platforms. Hole mobility in the range 450 cm(2)/Vs has been achieved on bulk germanium, but mobility is reduced during the densification of thinner dielectrics at 600 degrees C. This may be due to the formation of volatile GeO at the interface during densification. Low temperature measurements of the thinner dielectric device indicate that lattice scattering is dominant at room temperature for the device where the densification was omitted and the excellent subthreshold slopes at low temperatures also indicate devices of good quality.

引用

页码：43 / 49

页数：7

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