A novel approach to characterization of progressive breakdown in high-k/metal gate stacks

被引：34

作者：

Pagano, R. ^{[1
]}

Lombardo, S. ^{[1
]}

Palumbo, F. ^{[2
]}

Kirsch, P. ^{[3
,4
]}

Krishnan, S. A. ^{[3
,4
]}

Young, C. ^{[3
]}

Choi, R. ^{[3
]}

Bersuker, G. ^{[3
]}

Stathis, J. H. ^{[4
]}

机构：

[1] CNR, IMM, I-95121 Catania, Italy

[2] CNEA, CONICET, Buenos Aires, DF, Argentina

[3] SEMATECH, Austin, TX 78741 USA

[4] IBM Res Div, Yorktown Hts, NY 10598 USA

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 11-12期

关键词：

D O I：

10.1016/j.microrel.2008.07.071

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO2/interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1759 / 1764

页数：6

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