Synthesis of Multiple Valued Logic Digital Circuits using CMOS Gates

In Digital electronics to build a chip using Binary-logic, large area and more number of interconnections are required. One of the solutions is to use a larger set of signals over the same chip area. In this way Multiple-Valued Logic Designs are gaining importance. This paper presents multiple-valued multiplexer, full adder and single bit memory element. This design uses SUC (successor), MAX (Maximum) and eANDx (extended AND1, extended AND2 and extended AND3) operators. Application of multi-valued (non-binary) digital signals can provide considerable relief for a number of problems faced using the binary systems. Increased information density and processing efficiency of circuits could theoretically be substantially increased without any drastic increase in the cost of the underlying fabrication technology through the use of MultipleValued Logic (MVL). The use of non-binary data storage (ROM, RAM, Flash Memory) has led to reduction in on-chip physical space as compared to the use of binary data storage. Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Tanner EDA tool using TSMC 0.3 mu m technology and have shown improvements in performance and power consumption and propagation delay than their equivalent binary circuits.