A Floorplan Method for ASIC Designs of Asynchronous Circuits with Bundled-data Implementation

被引：0

作者：

Iizuka, Minoru ^{[1
]}

Saito, Hiroshi ^{[1
]}

机构：

[1] Univ Aizu, Aizu Wakamatsu, Fukushima 9658580, Japan

来源：

2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This study proposes a floorplan method for asynchronous circuits with bundled-data implementation to support ASIC designs. The proposed method based on Simulated Annealing (SA) and sequence-pair minimizes both latency and chip size of bundled-data implementation considering setup constraints. In the experiments, the floorplan results obtained by the proposed method are evaluated in terms of latency and chip size by changing parameters of SA and weights for latency and chip size.

引用

页数：4

共 46 条

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