A Floorplan Method for ASIC Designs of Asynchronous Circuits with Bundled-data Implementation

被引：0

作者：

Iizuka, Minoru ^{[1
]}

Saito, Hiroshi ^{[1
]}

机构：

[1] Univ Aizu, Aizu Wakamatsu, Fukushima 9658580, Japan

来源：

2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This study proposes a floorplan method for asynchronous circuits with bundled-data implementation to support ASIC designs. The proposed method based on Simulated Annealing (SA) and sequence-pair minimizes both latency and chip size of bundled-data implementation considering setup constraints. In the experiments, the floorplan results obtained by the proposed method are evaluated in terms of latency and chip size by changing parameters of SA and weights for latency and chip size.

引用

页数：4

共 46 条

[1] A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation on FPGAs
Saito, Hiroshi
Hamada, Naohiro
Yoneda, Tomohiro
Nanya, Takashi
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 925 - 928
[2] A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementation
Hamada, Naohiro
Shiga, Yuuki
Saito, Hiroshi
Yoneda, Tomohiro
Myers, Chris
Nanya, Takashi
2008 8TH INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN, PROCEEDINGS, 2008, : 50 - +
[3] A control circuit synthesis method for asynchronous circuits in bundled-data implementation
Konishi, Takao
Hamada, Naohiro
Saito, Hiroshi
2007 CIT: 7TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY, PROCEEDINGS, 2007, : 847 - +
[4] A Tool Set for the Design of Asynchronous Circuits with Bundled-data Implementation
Iizuka, Minoru
Hamada, Naohiro
Saito, Hiroshi
Yamaguchi, Ryoichi
Yoshinaga, Minoru
2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2011, : 78 - 83
[5] A behavioral synthesis system for asynchronous circuits with bundled-data implementation
Hamada, Naohiro
Shiga, Yuki
Konishi, Takao
Saito, Hiroshi
Yoneda, Tomohiro
Myers, Chris
Nanya, Takashi
IPSJ Transactions on System LSI Design Methodology, 2009, 2 : 64 - 79
[6] An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation
Iizuka, Minoru
Hamada, Naohiro
Saito, Hiroshi
IEICE TRANSACTIONS ON ELECTRONICS, 2013, E96C (04) : 482 - 491
[7] Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
Hamada, Naohiro
Saito, Hiroshi
IEICE TRANSACTIONS ON ELECTRONICS, 2012, E95C (04): : 506 - 515
[8] Static Timing Analysis of Asynchronous Bundled-Data Circuits
Gimenez, Gregoire
Cherkaoui, Abdelkarim
Cogniard, Guillaume
Fesquet, Laurent
2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC), 2018, : 110 - 118
[9] A cost-effective handshake protocol and its implementation for bundled-data asynchronous circuits
Shimizu, M
Abe, K
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (01) : 280 - 287
[10] A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-data Model
Sato, Shuichi
Ohtake, Satoshi
2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015), 2015, : 243 - 248

← 1 2 3 4 5 →