Design of a 16-bit real time stack processor in FPGA

被引:0
|
作者
Du, YC [1 ]
机构
[1] Northeastern Univ, Shenyang 110004, Peoples R China
关键词
FPGA; stack processor; state machine; behavioral description;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The basic structure and features of a 16-bit real time stack. processor is introduced. The design and implementation method of the 16-bit stack processor is presented in the paper. The behavioral description and state machine description is applied to program design using VHDL. The 16-bit real time stack processor implemented by Spartan-II XC2S200 FPGA chip, and is successfully adopted in frequency spectrum controller system of MRI.
引用
收藏
页码:726 / 729
页数:4
相关论文
共 50 条
  • [31] A MICROPROCESSOR EDUCATION-PROGRAM THAT BEGINS WITH A 16-BIT PROCESSOR
    RICHARDSON, A
    CHALLENGES OF A CHANGING WORLD, VOLS 1 AND 2, 1991, : 807 - 811
  • [32] A 16-bit parallel MAC architecture for a multimedia RISC processor
    Kuroda, I
    Murata, E
    Nadehara, K
    Suzuki, K
    Arai, T
    Okamura, A
    1998 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS-SIPS 98: DESIGN AND IMPLEMENTATION, 1998, : 103 - 112
  • [33] A 16-BIT X 16-BIT PIPELINED MULTIPLIER MACROCELL
    HENLIN, DA
    FERTSCH, MT
    MAZIN, M
    LEWIS, ET
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (02) : 542 - 547
  • [34] Real-time operating system (RTOS) for small (16-bit) microcontroller
    Tan, Su-Lim
    Anh, Tran Nguyen Bao
    ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2, 2009, : 128 - +
  • [35] Design, development and testing of a 16-bit reduced instruction set computer architecture based processor
    Manan Jain
    Het Kanzariya
    Neel Joshi
    Yesha Masharu
    Sachin Gajjar
    Dhaval Shah
    Sādhanā, 48
  • [36] Design, development and testing of a 16-bit reduced instruction set computer architecture based processor
    Jain, Manan
    Kanzariya, Het
    Joshi, Neel
    Masharu, Yesha
    Gajjar, Sachin
    Shah, Dhaval
    SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2023, 48 (04):
  • [37] Design of a 16-Bit Harvard Structure RISC Processor in Cadence 45nm Technology
    Venkatesan, Chandran
    Sulthana, Thabsera M.
    Sumithra, M. G.
    Suriya, M.
    2019 5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION SYSTEMS (ICACCS), 2019, : 173 - 178
  • [38] Design of Efficient 16-bit Vedic Multiplier
    Chowdary, K. Keshav Sai
    Mourya, K.
    Teja, S. Ravi
    Babu, G. Suresh
    Priya, S. Sridevi Sathya
    ICSPC'21: 2021 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICPSC), 2021, : 214 - 218
  • [39] 8-BIT AND 16-BIT PROCESSOR FAMILY KEEPS PACE WITH FAST RAMS
    CARTER, W
    HU, J
    LYNCH, F
    STEVENSON, D
    ELECTRONIC DESIGN, 1983, 31 (09) : 215 - 221
  • [40] 16-Bit Teaching Microprocessor Design and Application
    Tiejun, Xiao
    Fang, Liu
    2008 IEEE INTERNATIONAL SYMPOSIUM ON IT IN MEDICINE AND EDUCATION, VOLS 1 AND 2, PROCEEDINGS, 2008, : 160 - 163