An ADPLL with a MASH 1-1-1 ΔΣ Time-Digital Converter

An all digital phase-locked loop with a frequency range of 2.35 similar to 2.55 GHz is presented. A MASH 1-1-1 Delta Sigma time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm(2) of area.