An ADPLL with a MASH 1-1-1 ΔΣ Time-Digital Converter

被引：0

作者：

Wang, Zixuan ^{[1
]}

Huang, Cheng ^{[1
]}

Wu, Jianhui ^{[1
]}

机构：

[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Nanjing 210096, Jiangsu, Peoples R China

来源：

2014 17TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (MELECON) | 2014年

关键词：

all digital phase-locked loop; delta-sigma time-digital converter; noise shaping; digitally controlled oscillator; FREQUENCY-SYNTHESIZER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all digital phase-locked loop with a frequency range of 2.35 similar to 2.55 GHz is presented. A MASH 1-1-1 Delta Sigma time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm CMOS process exhibits a phase noise of -122 dBc/Hz @1MHz offset at a frequency of 2.48 GHz and a power dissipation of 11 mW under a supply of 1.2 V. The core occupied 0.49 mm(2) of area.

引用

页码：266 / 270

页数：5

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