Using EventB to Create a Virtual Machine Instruction Set Architecture

被引:0
|
作者
Wright, Stephen [1 ]
机构
[1] Univ Bristol, Dept Comp Sci, Bristol BS8 1TH, Avon, England
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine, a well-known example being the Java Virtual Machine (JVM). Despite there being many binary Instruction Set Architectures (ISA) in existence, all share a set of core properties which have been tailored to their particular applications. An abstract model may capture these generic properties and be subsequently refined to a particular machine, providing a reusable template for development of formally proven ISAs: this is a task to which the EventB [16,181 notation is well suited. This paper describes a project to use the RODIN tool-set [24] to perform such a process, ultimately producing the MIDAS (Microprocessor Instruction and Data Abstraction System) VM, capable of running binary executables compiled From high-level languages such as C [9]. The abstract model is incrementally refined to a model capable of automatic translation to C source code, and compilation for a hardware platform using a standard compiler. A second C compiler, targeted to the VM itself, allows C programs to be executed on it.
引用
收藏
页码:265 / 279
页数:15
相关论文
共 50 条
  • [31] Disentangling virtual machine architecture
    Haupt, M.
    Adams, B.
    Timbermont, S.
    Gibbs, C.
    Coady, Y.
    Hirschfeld, R.
    IET SOFTWARE, 2009, 3 (03) : 201 - 218
  • [32] The architecture of a UML virtual machine
    Riehle, D
    Fraleigh, S
    Bucka-Lassen, D
    Omorogbe, N
    ACM SIGPLAN NOTICES, 2001, 36 (11) : 327 - 341
  • [33] SCISM: A scalable compound instruction set machine
    Vassiliadis, S., 1600, (38):
  • [34] SCISM - A SCALABLE COMPOUND INSTRUCTION SET MACHINE
    VASSILIADIS, S
    BLANER, B
    EICKEMEYER, RJ
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1994, 38 (01) : 59 - 78
  • [35] A Quantum Pipeline for an Executable Quantum Instruction Set Architecture
    Batabyal, Suvadip
    Sharma, Lovekush
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 294 - 299
  • [36] REDUCED INSTRUCTION SET ARCHITECTURE FOR A GAAS MICROPROCESSOR SYSTEM
    FOX, ER
    KIEFER, KJ
    VANGEN, RF
    WHALEN, SP
    COMPUTER, 1986, 19 (10) : 71 - 80
  • [37] Effective compilation support for variable instruction set architecture
    Liu, J
    Kong, T
    Chow, F
    2002 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 2002, : 56 - 67
  • [38] Design of architecture and instruction-set of RASIP for SDR
    Raju, K. Solomon
    Kartikeyan, M. V.
    Joshi, R. C.
    Shekhar, Chandra
    2006 INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATIONS, VOLS 1 AND 2, 2007, : 480 - +
  • [39] PIPS: An Instruction Set Architecture for Teaching Computer Organization
    Curtsinger, Charlie
    Weinman, Jerod
    2021 ACM/IEEE WORKSHOP ON COMPUTER ARCHITECTURE EDUCATION (WCAE), 2021,
  • [40] Variable instruction set architecture and its compiler support
    Liu, J
    Chow, F
    Kong, T
    Roy, R
    IEEE TRANSACTIONS ON COMPUTERS, 2003, 52 (07) : 881 - 895