Using EventB to Create a Virtual Machine Instruction Set Architecture

被引:0
|
作者
Wright, Stephen [1 ]
机构
[1] Univ Bristol, Dept Comp Sci, Bristol BS8 1TH, Avon, England
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine, a well-known example being the Java Virtual Machine (JVM). Despite there being many binary Instruction Set Architectures (ISA) in existence, all share a set of core properties which have been tailored to their particular applications. An abstract model may capture these generic properties and be subsequently refined to a particular machine, providing a reusable template for development of formally proven ISAs: this is a task to which the EventB [16,181 notation is well suited. This paper describes a project to use the RODIN tool-set [24] to perform such a process, ultimately producing the MIDAS (Microprocessor Instruction and Data Abstraction System) VM, capable of running binary executables compiled From high-level languages such as C [9]. The abstract model is incrementally refined to a model capable of automatic translation to C source code, and compilation for a hardware platform using a standard compiler. A second C compiler, targeted to the VM itself, allows C programs to be executed on it.
引用
收藏
页码:265 / 279
页数:15
相关论文
共 50 条
  • [1] An Instruction Set Architecture for Machine Learning
    Chen, Yunji
    Lan, Huiying
    Du, Zidong
    Liu, Shaoli
    Tao, Jinhua
    Han, Dong
    Luo, Tao
    Guo, Qi
    Li, Ling
    Xie, Yuan
    Chen, Tianshi
    ACM TRANSACTIONS ON COMPUTER SYSTEMS, 2019, 36 (03):
  • [2] Managing changes to a packet-processing virtual machine's instruction set architecture over time
    Duncan, Ralph
    INTERNATIONAL JOURNAL OF COMPUTATIONAL SCIENCE AND ENGINEERING, 2019, 20 (02) : 166 - 178
  • [3] LLVA: A low-level virtual instruction set architecture
    Adve, V
    Lattner, C
    Brukman, M
    Shukla, A
    Gaeke, B
    36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, 2003, : 205 - 216
  • [4] Encoding the Java']Java Virtual Machine's Instruction Set
    Eichberg, Michael
    Sewe, Andreas
    ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE, 2010, 264 (04) : 35 - 50
  • [5] The Java Virtual Machine in retargetable, high-performance instruction set simulation
    Kaufmann, Marco
    Häsing, Matthias
    Preußer, Thomas
    Spallek, Rainer
    Proceedings of the 9th International Conference on the Principles and Practice of Programming in Java, PPPJ 2011, 2011, : 21 - 30
  • [6] Minimal Instruction Set AES Processor using Harvard Architecture
    Kong, J. H.
    Ang, L. -M.
    Seng, K. P.
    PROCEEDINGS OF 2010 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGY, VOL 9 (ICCSIT 2010), 2010, : 65 - 69
  • [7] Loongson Instruction Set Architecture Technology
    Hu W.
    Wang W.
    Wu R.
    Wang H.
    Zeng L.
    Xu C.
    Gao X.
    Zhang F.
    Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2023, 60 (01): : 2 - 16
  • [8] DISTRIBUTED INSTRUCTION SET COMPUTER ARCHITECTURE
    WANG, L
    WU, CL
    IEEE TRANSACTIONS ON COMPUTERS, 1991, 40 (08) : 915 - 934
  • [9] Parallelism and the ARM instruction set architecture
    Goodacre, J
    Sloss, AN
    COMPUTER, 2005, 38 (07) : 42 - +
  • [10] REDUCED INSTRUCTION SET COMPUTER ARCHITECTURE
    STALLINGS, W
    PROCEEDINGS OF THE IEEE, 1988, 76 (01) : 38 - 55