State-Dependence of On-Chip Power Distribution Network Capacitance

被引：1

作者：

Yamanaga, Koh ^{[1
]}

Hagiwara, Shiho ^{[2
]}

Takahashi, Ryo ^{[3
]}

Masu, Kazuya ^{[4
]}

Sato, Takashi ^{[5
]}

机构：

[1] Murata Mfg Co Ltd, Kyoto 6178555, Japan

[2] Fujitsu Labs Ltd, Kawasaki, Kanagawa 2118588, Japan

[3] Univ Tokyo, Inst Ind Sci, Tokyo 1538585, Japan

[4] Tokyo Inst Technol, Solut Res Lab, Yokohama, Kanagawa 2268503, Japan

[5] Kyoto Univ, Grad Sch Informat, Kyoto 6068501, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2014年 / E97C卷 / 01期

关键词：

CMOS logic circuit; state-dependent capacitance model; capacitance measurement; PDN-capacitance; parasitic capacitance;

D O I：

10.1587/transele.E97.C.77

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance.

引用

页码：77 / 84

页数：8

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