A comparison of architectures for a programmable fuzzy logic chip

被引：0

作者：

Lund, T ^{[1
]}

Torralba, A ^{[1
]}

Carvajal, RG ^{[1
]}

Ramirez-Angulo, J ^{[1
]}

机构：

[1] Univ Canberra, Fac Informat Sci & Engn, Canberra, ACT 2601, Australia

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: SYSTEMS, POWER ELECTRONICS, AND NEURAL NETWORKS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Three possible architectures for a programmable fuzzy logic chip are proposed and examined in terms of their implications for implementation. The capabilities of each architecture in terms of number of inputs and outputs usable, and the number of membership functions available for each of these, the size of the possible rule base, and the versatility and programmability of the design, are weighed against the chip area required, the likely power consumption, and the accuracy and throughput.

引用

页码：623 / 626

页数：4

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