Educating Hardware Design - From Boolean Equations to Massively Parallel Computing Systems

被引:0
|
作者
Knodel, Oliver [1 ]
Zabel, Martin [1 ]
Lehmann, Patrick [1 ]
Spallek, Rainer G. [1 ]
机构
[1] Tech Univ Dresden, Dept Comp Sci, D-01062 Dresden, Germany
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中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. In this paper we present lectures and especially practical FPGA design courses for bachelor and master students. We introduce a selection of individual projects, which were realized by students in practical courses. With examples from final bachelor projects and master theses we demonstrate the quality of education and its integration into current research. We describe possible improvements of labs, such as automated test benches and a remote FPGA laboratory for advanced courses.
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页数:6
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