Fault tolerant system based on IDDQ testing

被引:1
|
作者
Guibane, Badi [1 ]
Hamdi, Belgacem [1 ]
Mtibaa, Abdellatif [1 ]
Bensalem, Brahim [2 ]
机构
[1] Univ Monastir, Fac Sci Monastir, Elect & Microelect LAB, Monastir, Tunisia
[2] Intel Corp, Interconnect R&D Grp, Folsom, CA USA
关键词
Built-in current sensor; design for testability; IDDQ testing; analogue and mixed circuits; integrated test; circuit under test; RELIABLE COMPUTATION; YIELD IMPROVEMENT; NOISY GATES; CIRCUITS; REDUNDANCY; FORMULAS; DESIGN; BOUNDS;
D O I
10.1080/00207217.2018.1426113
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.
引用
收藏
页码:1025 / 1035
页数:11
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