Hardware implementation of the QC-LDPC decoder in the FPGA structure

被引：0
|
作者：
Kuc, Mateusz [1 ,2 ]
Sulek, Wojciech [1 ,2 ]
Kania, Dariusz [1 ,2 ]
机构：
[1] Politechn Slaska, Inst Elekt, Gliwice, Poland
[2] Inst Elekt, Ul Akad 16, PL-44100 Gliwice, Poland
来源：
PRZEGLAD ELEKTROTECHNICZNY | 2020年 / 96卷 / 09期
关键词：
QC-LDPC; FPGA; Min-Sum; Normalized MM-Sum; 802.11ad; 802.16e; WiGig; WiMax;
D O I：
10.15199/48.2020.09.03
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper presents hardware implementation of QC-LDPC decoder (Quasi-Cyclic Low-density Parity-Check) in FPGA structure. In the presented decoder, Min-Sum and Normalized Min-Sum algorithms can be utilized. Normalization in the Normalized Min-Sum algorithm is performed using Lookup Tables (LUTs). a comparison of decoder operating with different data bus sizes is also shown. All presented results were obtained in the Intel Cyclone V system for 802.11ad (WiGig) and 802.We (WiMax) standards.
引用
收藏
页码：16 / 20
页数：5
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