共 50 条
- [32] SE Performance of a Schmitt-Trigger-Based D-Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
- [33] Source Mask Optimization based on Design Pattern Library at 7nm Technology Node DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION XV, 2021, 11614
- [35] CDM Protection Design using Internal Power Node for Cross Power Domain in 16nm CMOS Technology 2016 38TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2016,
- [37] Analog Circuit and Device Interaction in High-Speed SerDes Design in 16nm FinFET CMOS Technology 2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2014,
- [38] A scaled floating body cell (FBC) memory with high-k plus metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond 2008 SYMPOSIUM ON VLSI TECHNOLOGY, 2008, : 71 - +
- [39] A scaled floating body cell (FBC) memory with High-k plus metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond 2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, : 92A - 93A
- [40] Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (09): : 4099 - 4109