Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis

被引：0

作者：

Fukaya, Kosuke ^{[1
]}

Mori, Kaito ^{[1
]}

Imamura, Kousuke ^{[2
]}

Matsuda, Yoshio ^{[2
]}

Matsumura, Tetsuya ^{[3
]}

Mochizuki, Seiji ^{[1
]}

机构：

[1] Nihon Univ, Grad Sch Engn & Technol, Koriyama, Fukushima, Japan

[2] Kanazawa Univ, Inst Sci & Engn, Kanazawa, Ishikawa, Japan

[3] Nihon Univ, Coll Engn, Koriyama, Fukushima, Japan

来源：

2019 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS) | 2019年

关键词：

video coding; low latency; autonomous driving; virtual reality (VR); FPGA;

D O I：

10.1109/ispacs48206.2019.8986365

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

For real-time applications such as autonomous driving and virtual reality (VR), we previously proposed an ultra-low-latency video coding method, which adopts line-based processing for Full-HD video. In this paper, we newly propose a design and implementation of the ultra-low-latency video encoder. In order to reduce the hardware amount, image-prediction specification is optimized for our previous work. Applying a high-level synthesis (HLS) design methodology for Xilinx FPGA, the implementation results of logic count with 10,677 LUTs, 3,714FFs and 66 DSPs is obtained. The implemented video encoder achieves less than 1.0 mu s low-latency and compression to 39.4% without significant visual degradation. As a result, cost effective ultra-low-latency video encoder is implemented for low cost FPGA.

引用

页数：2

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