A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm

被引：0

作者：

Li, Bingyi ^{[1
,2
]}

Fang, Linlin ^{[1
,2
]}

Xie, Yizhuang ^{[1
,2
]}

Chen, He ^{[1
,2
]}

Chen, Liang ^{[1
,2
]}

机构：

[1] Beijing Inst Technol, Sch Informat & Elect, Radar Res Lab, Beijing, Peoples R China

[2] Beijing Key Lab Embedded Real Time Informat Proc, Beijing, Peoples R China

来源：

2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) | 2017年

关键词：

reconfigurable; floating-point; CORDIC; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design methodology and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architecture that can be configured to operate in different modes and rotations to achieve single-precision floating point division, multiplication and square-root operations. Through introducing pre- and post- processing, the float-point operations can be integrated into a unified CORDIC iteration procedure. According to the characteristics of different operations, we propose a pipeline-parallel mixed architecture to optimize the area-delay-efficiency. Finally, the prototype based on Xilinx XC7VX690T has been established to test the performance of the proposed design. The result shows the related error with arithmetic computation is less than 10(-6), and the resource-consumption of the proposed design is less than the sum of existing IP cores.

引用

页码：301 / 302

页数：2

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